Instantaneous phase detecting circuit and clock recovery signal generating circuit incorporated in differential demodulator

ABSTRACT

A clock recovery signal generating circuit for generating a clock recovery signal includes a plurality of detection axis cross detectors varied in magnitude of detection axis admitting a phase difference signal, for detecting the time at which the phase difference signal crosses the detection axis of a prescribed magnitude. A locus sorter discriminates and sorts the locus of a change in the phase difference signal based on the data of timing obtained by the detection axis cross detectors and generates a timing adjusting signal in conformity with the result of the sorting. Timing control generates a clock recovery signal by correcting the data of timing obtained by one of the plurality of detection axis cross detectors designated by the timing adjusting signal with the time designated by the timing adjusting signal.

TECHNICAL FIELD

This invention relates to an instantaneous phase detecting circuit and aclock recovery signal generating circuit which are incorporated in adifferential demodulator for π/4-shift QPSK signals.

BACKGROUND ART

As means of digital modulation for the digital mobile communication, theπ/4-shift QPSK method which carries out the modulation while shiftingthe phase axis by π/4 at a time for each symbol period (two bits, forexample) which forms one data unit has been adopted on account ofvarious advantages attendant thereon (literature 1). The differentialdemodulator of the π/4-shift QPSK method which realizes miniaturizationof the structure of modulation and economization of the powerconsumption has been also proposed (literature 2).

Literature 1: "Proposal of Linear Modulation Method for Digital MobileCommunication," No. 2348, written jointly by Yoshihiko Akaiwa andYoshiki Nagata and presented at the 1985 Consolidated National Meetingof Electronic Communication Society

Literature 2: "λ/4-Shift QPSK Differential Demodulator for DigitalCordless Telephone," No. B-344, written jointly by Hiroshi Shida,Tsutomu Suda, and Kenzo Urabe and presented at the 1992 Spring GeneralMeeting of Electronic Data Communication Society

FIG. 16 represents a block diagram of the conventional differentialdemodulator which is disclosed in literature 2.

Now, the differential demodulator for the modulation of a π/4-shift QPSKsignal will be described below with reference to FIG. 16.

The differential demodulator comprises an input terminal 1, anoscillator 2, an instantaneous phase detecting circuit 3, a phasedifference computing circuit 5, a clock recovery circuit 7, a dataregenerating circuit 8, a clock recovery signal output terminal 9, and aregenerating data output terminal 10.

The input terminal 1 admits a modulation wave (carrier wave) signal (10,7 MHz, for example) which has been modulated by the π/4-shift QPSKmethod.

The oscillator 2 generates an electric oscillation which is asynchronouswith and substantially equal in frequency to the modulated signalintroduced to the input terminal 1.

FIG. 17 represents a block diagram of the conventional instantaneousphase detecting circuit 3. The instantaneous phase detecting circuit 3is composed of an exclusive OR (hereinafter "EX-OR") circuit 171, a Dtype flip-flop (hereinafter "DFF") circuit 172, an analog low-passfilter (hereinafter "LPF") 173, an analog/digital converter (hereinafter"A/D converter") 174, and a polarity switching circuit 175.

Now, the operation of the instantaneous phase detecting circuit 3 willbe described below with reference to FIG. 18.

FIG. 18a represents phase detection characteristics which have beenprocessed by the EX-OR circuit 171 and the LPF 173. In the diagram, theperiods of 0-π, 2π-3π, and 4π-5π have an upwardly slanting phasedetection characteristic and the periods of π-2π, 3π-4π, and 5π-6π havea downwardly slanting phase detection characteristic respectively to theright. FIG. 18b represents the phase detection characteristics of theDFF circuit 172. In the diagram, the periods of 0-π, 2π-3π, and 4π-5πhave a phase detection characteristic of 1 and the periods of π-2π,3π-4π, and 5π-6π have a phase detection characteristic of 0.

The output of FIG. 18a is emitted as it is when the output from the DFFcircuit 172 is 1. The output of FIG. 18a is emitted with the signthereof inverted when the output from the DFF circuit 172 is 0. As aresult, a linear phase detection is effected over the periods of from πto 3π and to 2π as shown in FIG. 18c.

The clock recovery circuit 7 is composed of a clock recovery signalgenerating circuit 71 and a digital phase locked loop (hereinafter"DPLL") 72 as shown in FIG. 19. The clock recovery signal generatingcircuit 71 is composed of a magnitude comparator 711 and a level settingcircuit 712.

FIG. 20 represents the relation between the conventional clock recoverysignal and the eye pattern. The term "eye pattern" refers to a figurederived from the loci of a phase difference signal 6 which are describedby all the patterns possibly assumed by the phase difference signal 6.The expression "the eye pattern is opened" as used herein refers to thestate in which figures enclosed with one phase difference signal 6 andanother phase difference signal 6 assume the shape of a human eye. Theexpression "the eye pattern is closed" refers to the state in whichfigures enclosed with such phase difference signals 6 assume a decreasedarea.

The conventional instantaneous phase detecting circuit 3, however,relies for phase discrimination on the DFF circuit 172. The phasediscrimination by the DFF circuit 172 lasts only during the instant ofinitiation of the signal admitted into the clock terminal. When theinput modulation wave has a low frequency, namely when the frequency ofthe oscillator 2 is low (as, for example, when a frequency of 1.2 MHz isused), therefore, the intervals of polarity discrimination are too wideto coincide with the phase discrimination of FIG. 18a. The phasediscrimination in this case, therefore, is at a disadvantage in breakingthe continuity of the phase detection in the neighborhood of π, 2π, . .. , nπ (n for an integer).

Further, the conventional clock recovery signal generating circuit 71entails jitters ±δ as shown in FIG. 20b. It has the problem ofdeveloping a deadlock and consequently failing to effect the recoversatisfactorily, therefore, when the recovered clock signal by the DPLL72 has a difference of 180° from the phase of the phase differencesignal 6. The term "jitters" as used herein refers to fluctuations ofthe phase difference signal 6 relative to the clock signal.

With reference to the diagram of FIG. 20a, the jitters are substantiallyeffaced by setting the detection level during the period of preamble atlevel 2 (phase difference of π/4) and returning the detection level tolevel 1 (phase difference of 0) after termination of the period ofpreamble. This method, however, entails the necessity of discerningwhether the data currently received are those of preamble, those of UW,or those of data proper. The discrimination of sorts of data provesappreciably difficult and requires use of such an external circuit as amicroprocessor and can never be realized by a simple circuitconfiguration. The external microprocessor is so busy in realizing otherfunctions of processing that it cannot be easily utilized fordiscriminating sorts of data. As a result, it is difficult to adopt themethod which resorts to switching the set levels depending on the sortsof data mentioned above.

It is an object of this invention to provide an instantaneous phasedetecting circuit which precludes discontinuation of phase and givesrise to no inconvenience in response to a decrease in the frequency ofthe input modulation wave. It is another object of this invention toprovide an instantaneous phase detecting circuit which is composed ofinvariably digital circuits and has no use for the analog LPF 173 andthe A/D converter 174 which have been heretofore found as indispensablecomponents.

It is further object of this invention to provide a clock recoverysignal generating circuit which generates such a clock recovery signalas is capable of ideally effecting the recovery at the time that theDPLL leads in a clock signal or even after it has led in the clocksignal.

DISCLOSURE OF THE INVENTION

First, the instantaneous phase detecting circuit of this invention ischaracterized by comprising a first logic arithmetic circuit foradmitting a modulation wave signal and a carrier, performing a logicaloperation using the two input signals, and emitting a first result ofarithmetic operation, a second logic arithmetic circuit for admittingthe modulation wave signal and a signal having the phase of the carrierdelayed by a fixed period, performing a logical operation using the twoinput signals, and emitting a second result of arithmetic operation, afirst phase detecting circuit for admitting the first result ofarithmetic operation and the carrier, detecting the phase of the firstresult of arithmetic operation, and emitting a first result ofdetection, a second phase detecting circuit for admitting the secondresult of arithmetic operation and the carrier, detecting the phase ofthe second result of arithmetic operation, and emitting a second resultof detection, and a third logic arithmetic circuit for admitting thefirst and the second result of detection and comparing the two inputsignals by the use of the deviation of period between the two inputsignals thereby detecting the phase of the modulation wave signal.

The clock recovery signal generating circuit of this invention for thegeneration of a clock recovery signal is characterized by comprising aplurality of detection axis cross detecting means having detection axesvaried in magnitude and severally serving to admit a phase differencesignal and detect the time at which the phase difference signal crossesthe detection axis of a prescribed magnitude, locus sorting means fordiscriminating and sorting the locus of a change in the phase differencesignal based on the data of timing obtained by the detection axis crossdetecting means and emitting a timing adjusting signal in conformitywith the result of the sortation, and timing control means forgenerating a clock regenerating signal by correcting the detectiontiming obtained by one of the plurality of detection axis crossdetecting means designated by the timing adjusting signal with the timedesignated by the timing adjusting signal.

The clock recovery signal generating circuits according to the presentinvention are constructed as follows.

Specifically, they each comprise a plurality of detection axis crossdetecting means having detection axes varied in magnitude and serving todetect the time at which the phase difference signal crosses thedetection axis of a prescribed magnitude, a locus sorting means fordiscriminating and sorting the locus of a change in the phase differencesignal based on the data on detection timing obtained by the detectionaxis cross detecting means and emitting a timing adjusting signal inconformity with the result of the sortation, and a timing control meansfor correcting the detection timing obtained by one of the plurality ofdetection axis cross detecting means designated by the timing adjustingsignal with the time designated by the timing adjusting signal and usingthe result of the correction as a phase signal for clock recovery.

It is desirable that the construction described above is furtherprovided with phase difference discriminating means capable of detectingthe fact that the difference between the phase of the recovered clocksignal and the phase of the clock recovery phase signal has fallen belowa prescribed magnitude and, at the same time, the locus sorting means isso adapted as to effect the relevant processing exclusively by the useof the detection timing obtained by one of the plurality of detectionaxis cross detecting means when the phase discriminating means hasperformed an action of detection.

In the clock recovery signal generating circuit of this invention, theplurality of detection axis cross detecting means severally detect thetimes at which the phase difference signal admitted in the circuitcrosses the detection axes of magnitudes prescribed severally thereforand inform the locus sorting means of the detected times. The locussorting means discriminates and sorts the locus of a change in the phasedifference signal based on the times detected by the detection axiscross detecting means and issues a timing adjusting signal in conformitywith the result of the sortation to the timing control means. The timingcontrol means corrects the detection timing obtained by one of thedetection axis cross detecting means designated by the timing adjustingsignal with the time designated by the timing adjusting signal anddelivers the result of the correction as a phase signal for clockregeneration to the DPPL.

In such a communication system as is adapted to operate by thetransmission of a fixed pattern for clock recovery, for example, thetiming control circuit is enabled by the adjustment with the timingadjusting signal to emit a phase signal for clock recovery during theperiod of the fixed pattern when the locus sorting means is caused inadvance to learn how to discriminate the period of this fixed patternfrom any other period. Even during any other period than the period ofthe fixed pattern, the phase signal for clock recovery free from jittercan be emitted with high probability, depending on the setting of thesortation of locus. As a result, the phase of the clock signal to beemitted from the DPLL gains in desirability and stability.

Here, phase difference discriminating means capable of detecting thefact that the difference between the phase of the recovered clock signaland the phase of the clock recovery phase signal has fallen below aprescribed magnitude is provided additionally and the locus sortingmeans is so adapted as to effect the relevant processing by exclusivelyusing the detection timing obtained by one of the plurality of detectionaxis cross detecting means when the phase difference discriminatingmeans has performed an action of detection. As a result, the phase ofthe clock signal can be quickly incorporated into the phase of the phasedifference signal and, at the same time, the stabilization of the clocksignal thus incorporated is realized with exalted infallibility.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an example of the instantaneousphase detecting circuit of the present invention.

FIG. 2 is a table showing an arithmetic operation pattern of acomparison circuit of the present invention.

FIG. 3 is a graph showing a first and a second phase detectioncharacteristic obtained by a motion averaging filter circuit and theresult of a processing with the instantaneous phase detecting circuit ofthe present invention.

FIG. 4 is a block diagram illustrating a first example of the clockrecovery signal generating circuit of the present invention.

FIG. 5 is a diagram showing the data to be used in the presentinvention.

FIG. 6 is a diagram showing the conditions of detection and the timingadjusting outputs.

FIG. 7 is a diagram showing the locus pattern of a phase differencesignal and the output timing adjustment of a clock recovery pulse andthe output timing.

FIG. 8a is a diagram showing the locus pattern of a phase differencesignal.

FIG. 8b is a diagram showing the locus pattern of a phase differencesignal.

FIG. 8c is a diagram showing the locus pattern of a phase differencesignal.

FIG. 8d is a diagram showing the locus pattern of a phase differencesignal.

FIG. 8e is a diagram showing the locus pattern of a phase differencesignal.

FIG. 9 is a block diagram illustrating a second example of the clockrecovery signal generating circuit of the present invention.

FIG. 10 is a diagram showing the conditions of detection and the timingadjusting output.

FIG. 11 is a block diagram illustrating a third example of the clockrecovery signal generating circuit of the present invention.

FIG. 12 is a block diagram illustrating a fourth example of the clockrecovery signal generating circuit of the present invention.

FIG. 13 is a diagram showing the locus pattern of a phase differencesignal and the timing of generation of a pulse.

FIG. 14 is a diagram showing the locus pattern of a phase differencesignal and the timing of generation of a pulse.

FIG. 15 is a diagram showing the present clock signal and the clocksignals delayed by π/4 and advanced by π/4 respectively from the presentclock signal.

FIG. 16 is a block diagram illustrating a conventional differentialdemodulator.

FIG. 17 is a block diagram illustrating a conventional instantaneousphase detecting circuit.

FIG. 18 is a diagram showing the phase detection characteristicresulting from the processing by an EX-OR circuit and an LPF, the phasedetection characteristic of a DFF circuit, and a linear phase detectioncharacteristic.

FIG. 19 is a diagram showing a conventional clock recovery circuit.

FIG. 20 is a diagram showing the locus pattern of a phase differencesignal and the output timing of a conventional clock recovery signal.

BEST MODE OF EMBODYING THE INVENTION

First, an example of the instantaneous phase detecting circuit of thepresent invention will be explained in detail below with reference tothe accompanying drawings.

FIG. 1 is a block diagram illustrating in detail the construction of aninstantaneous phase detecting circuit 3A of the present invention. Theinstantaneous phase detecting circuit 3A is composed of a 1/n frequencydivider 21, EX-OR circuits 31 and 32, a π/2 phase-shifter 33, motionaveraging filters 34 and 35, and a logic circuit 36.

The motion averaging filter 34 is composed of an N-stage shift register341, a comparator 342, and an up-down counter 343.

Similarly, the motion averaging filter 35 is composed of an N-stageshift register 351, a comparator 352, and an up-down counter 353.

To the 1/n frequency divider 21 is applied a carrier S2 generated froman oscillator 2. The 1/n frequency divider 21 serves to divide thecarrier S2 into 1/n frequency. Here, the 1/n frequency is substantiallyequal to the frequency of a modulation wave signal S1 applied through aninput terminal 1. Then, the 1/n frequency divider 21 issues a signal S21divided into the 1/n frequency to the EX-OR circuit 31 and the π/2phase-shifter 33.

To the π/2 phase-shifter 33 is applied the signal S21 divided into the1/n frequency. The π/2 phase-shifter 33 shifts the phase of the receivedsignal S21 with a delay of π/2. Then, the π/2 phase-shifter 33 generatesa signal S33 having a phase delayed by π/2 to the EX-OR circuit 32.

The EX-OR circuits 31 and 32 are severally composed of electriccircuits, semiconductor elements, etc.

To the EX-OR circuit 31 are applied a modulation wave signal S1 and thesignal S21 divided into the 1/n frequency. Then, the EX-OR circuit 31carries out an exclusive logical sum operation on the input modulationwave signal S1 and the signal S21 divided into the 1/n frequency. TheEX-OR circuit 31 subsequently issues the result of the exclusive logicalsum operation as a signal S31 to the motion averaging filter 34.

To the EX-OR circuit 32 are injected the modulation wave signal S1 andthe signal S33 having a phase delayed by π/2. Then, the EX-OR circuit 32carries out an exclusive logical sum operation on the input modulationwave signal S1 and the signal S33 having a phase delayed by π/2. TheEX-OR circuit 32 subsequently issues the result of the exclusive logicalsum operation as a signal S32 to the motion averaging filter 35.

The motion averaging filter 34 is composed of the N-stage shift register341, the comparator 342, and the up-down counter 343. Here, N stands fora natural number.

To the N-stage shift register 341 are applied the result of arithmeticoperation S31 and the carrier S2. Here, the carrier S2 is used as amaster clock for driving the motion averaging filter 34. Then, theN-stage shift register 341 issues the contents of a first stage 341A andthose of an N'th stage 341B to the comparator 342. This issuance of thecontents to the comparator 342 is carried out in accordance with thetiming of the carrier S2 as the master clock.

To the comparator 342 are applied the carrier S2 and the contents of thefirst stage 341A of the N-stage shift register 341 and those of the N'thstage 341B. Here again, the carrier S2 is utilized as a master clock.After the arithmetic operations mentioned above have been completed, thecomparator 342 issues the result of the arithmetic operations as asignal S342 to the up-down counter 343.

The arithmetical operation which is performed by the comparator 342 willbe explained below. The arithmetical processing so fulfilled by thecomparator 342 is broadly divided into the following three types (referto FIG. 2).

(1) The comparator 342 causes a +1 up count in the up-down counter 343when the first stage 341A of the N-stage shift register 341 has an inputof 1 and the N'th stage 341B thereof has a content of 0.

(2) The comparator 342 causes a -1 down count in the up-down counter 343when the first stage 341A of the N-stage shift register 341 has an inputof 0 and the N'th stage 341B thereof has a content of 1.

(3) The comparator 342 causes no change in the up-down counter 343 whenthe content of the first stage 341A of the N-stage shift register 341and that of the N'th stage 341B thereof are equal (namely when the firststage 341A has a content of 0 and the N'th stage 341B has a content of 0or when the first stage 341A has a content of 1 and the N'th stage 341Bhas a content of 1).

When the comparator 342 has performed the arithmetical processingdescribed above for one timing of the master clock, the number of "1's"existing in the second through N'th stages of the N-stage shift register341 is displayed in the up-down counter 343. The content of the up-downcounter 343, therefore, indicates the outcome of the processingperformed on the output from the EX-OR circuit 31 by the motionaveraging filter which functions to average the time constant,T=(N-1)/fc. In the formula, N stands for the number of stages in theshift register 341 and fc for the frequency of the oscillator 2.

The up-down counter 343 generates a phase detection characteristic(numerical value counted as instructed by the comparator 342) S34 as anoutput to the logic circuit 36.

Incidentally, one example of the motion averaging filter circuit 34 isdisclosed in JP-B-01-38,244.

To the N-stage shift register 351 are applied the result of arithmeticoperation S32 and the carrier S2. In this case, the carrier S2 isutilized as a master lock for driving the motion averaging filtercircuit 35. Then, the N-stage shift register 351 issues the content ofthe first stage 351A and the content of the N'th stage 351B as outputsto the comparator 352. This issuance of the outputs to the comparator352 is carried out in accordance with the timing of the carrier S2 as amaster clock.

To the comparator 352 are applied the carrier S2 and the content of thefirst stage 351A and that of the N'th stage 351B of the N-stage shiftregister 351. Again in this case, the carrier S2 is utilized as a masterclock. The comparator 352 issues the result of arithmetic operation S352as an output to the up-down counter 353.

The operation of the comparator 352 is identical with that of thecomparator 342.

The up-down counter 353 issues a phase detection characteristic(numerical value counted as instructed by the comparator 352) S35 as anoutput to the logic circuit 36.

To the logic circuit 36 are applied the phase detection characteristicS34 and the phase detection characteristic S35. In the logic circuit 36,the sign of the input phase detection characteristic S34 is reversed onthe basis of the input phase detection characteristic S35. When theinput phase detection characteristic S35 has a minus sign, for example,the logic circuit 36 reverses the sign of the input phase detectioncharacteristic to minus and emits the outcome of the sign reversion asan output. When the input phase detection characteristic S35 has a plussign, the logic circuit 36 generates the input phase detectioncharacteristic S34 in its unaltered form as an output.

Now, the operation of the instantaneous phase detecting circuit of thepresent invention will be described below with reference to FIG. 3.

FIG. 3a is a graph showing the phase detection characteristic S34 whichis obtained by the motion averaging filter 34. In FIG. 3a, the periodsof 0-π, 2π-3π, and 4π-5π describe straight lines inclined upward to theright and indicating an increase of the content of the up-down counter343 from 0 to N-1. The periods of π-2π, 3π-4π, and 5π-6π describestraight lines inclined downward to the right and indicating a decreaseof the content of the up-down counter 343 from N-1 to 0. In the graph,the horizontal axis is the scale of the phase difference between thesignal S21 divided into the 1/n frequency and the modulation wave signalS1 and the vertical axis is the scale of the content of the up-downcounter 343.

FIG. 3b is a graph showing the phase detection characteristic S35 whichis obtained by the motion averaging filter 35. The phase detectioncharacteristic S35 shown in FIG. 3b is delayed by a phase of π/2 fromthe phase detection characteristic S34 shown in FIG. 3a. This delay ofphase is due to the π/2 phase-shifter 33.

In FIG. 3b, the period of 0-π/2 describes a straight line inclinedupward to the right and indicating an increase of the content of theup-down counter 353 from N/2 to N-1. The periods of (3π/2)-(5π/2) and(7π/2)-(9π/2) describe straight lines inclined upward to the right andindicating an increase of the content of the up-down counter 353 from 0to N-1. The period of (11π/2)-6π describes a straight line inclinedupward to the right and indicating an increase of the content of theup-down counter 353 from 0 to N/2. Then, the periods of π/2-(3π/2),(5π/2)-(7π/2), and (9π/2)-(11π/2) describe straight lines inclineddownward to the right and indicating a decrease of the content of theup-down counter 353 from N-1 to 0. In the graph, the horizontal axis isthe scale of the phase difference between the signal S21 divided intothe 1/n frequency and the modulation wave signal S1 and the verticalaxis is the scale of the content of the up-down counter 353.

The logic circuit 36 treats the periods of 0-π, 2π-3π, and 4π-5π aspositive periods and the periods of π-2π, 3π-4π, and 5π-6π as negativeperiods on the basis of N/2 in the content of the up-down counter 353.

In the periods discriminated as positive periods in FIG. 3b, the logiccircuit 36 generates the phase detection characteristic S34 shown inFIG. 3a in its unaltered form as an output. Then, in the periodsdiscriminated as negative periods in FIG. 3b, the logic circuit 36 emitsthe phase detection characteristic S34 shown in FIG. 3a with an invertedsign as an output.

The graph shown in FIG. 3c is consequently obtained. In FIG. 3c, theperiod of 0-π describes a straight line inclined upward to the right andindicating an increase of the phase from 0 to π. The periods of π-3π and3π-5π describe straight lines inclined upward to the right andindicating an increase of the phase from -π to π. Then, the period of5π-6π describes a straight line inclined upward to the right andindicating an increase of the phase from -π to 0.

In consequence of the operation described above, the instantaneous phasedetecting circuit of the present invention processes the digital phasemodulation wave by the use of the two EX-OR circuits, the motionaveraging filter circuit, and the logic circuit so as to have one phasedelayed by π/2 from the other phase. Owing to this processing, theinstantaneous phase detecting circuit of this invention does not easilyencounter discontinuation of phase detection even when the modulationwave to be received as an input has such a low frequency as 1, 2 MHz.The instantaneous phase detecting circuit of this invention, therefore,is capable of effecting phase detection with accuracy.

This invention does not limit the delay of phase to π/2. It can belikewise embodied even when the delay is 0, π/4, etc., for example. Whenthe delay is so changed, the construction of the logic circuit 36 may besuitably altered in conformity with the particular delay of phase.

Since the instantaneous phase detecting circuit of this invention uses amotion averaging filter for its configuration as described above, it canbe digitized, adapted for integration of circuit, and allowed to enjoy acut in cost. The devices which use the instantaneous phase detectingcircuit of this invention, therefore, are at an advantage in attainingreduction in size and weight.

Now, the first example of the clock recovery signal generating circuitof the present invention will be described below with reference to theannexed drawings. FIG. 4 is a block diagram illustrating in detail theconstruction of the first example.

A clock recovery circuit 7A is composed of a clock recovery signalgenerating circuit 71A and the DPLL (digital phase locked loop) circuit72.

The clock recovery signal generating circuit 71A is composed ofmagnitude comparators 701 and 703, level setting circuits 702 and 704, alocus sorting circuit 710, and-a timing control circuit 707. The locussorting circuit 710 is composed of a timer circuit 705 and adiscriminating circuit 706. Here, the magnitude comparator 701 and thelevel setting circuit 702 are disposed correspondingly. The magnitudecomparator 703 and the level setting circuit 704 are also disposedcorrespondingly.

Now, the construction of the clock recovery signal generating circuit71A will be described below.

The magnitude comparators 701 and 703 are comparators of a sort for usewith digital circuits. The magnitude comparators 701 and 703 arecircuits for generating an instantaneous pulse when the phase differencesignal 6 received as an input equals the magnitude of detection level(detection axis) set in advance by the corresponding level settingcircuits 702 and 704.

The level setting circuit 702 and 704 set the magnitude of detectionlevel (detection axis) and generate the magnitude of detection level asan output to the magnitude comparators 701 and 703.

To the magnitude comparator 701 are injected the phase difference signal6 and a magnitude of detection level S702 issued from the level settingcircuit 702. The magnitude comparator 701 compares the input phasedifference signal 6 with an input magnitude of detection level S701 anddetermines whether or not they are equal. The magnitude comparator 701generates the pulse S701 (hereinafter the pulse S701 issued from themagnitude comparator 701 will be referred to briefly as "level 1 crosspulse S701") only when it has discriminated the equality between theinput phase difference signal 6 and the input magnitude of detectionlevel S702. When the magnitude comparator 701 has issued the level 1cross pulse S701, the magnitude comparator 701 generates the level 1cross pulse S701 as an output to the timing control circuit 707 and thelocus sorting circuit 710. Here, the level setting circuit 702 has level1 corresponding to a phase difference of 0 set as the magnitude ofdetection level S702 (refer to FIG. 6a and FIG. 7 which will bespecifically described hereinafter).

Similarly to the magnitude comparator 703 are applied the phasedifference signal 6 and a magnitude of detection level S704 to be issuedfrom the level setting circuit 704. The magnitude comparator 703determines whether or not the input phase difference signal 6 and theinput magnitude of detection level S704 are equal. The magnitudecomparator 703 issues a pulse S703 (hereinafter the pulse S703 issued bythe magnitude comparator 703 will be referred to briefly as "level 0cross pulse S703") only when it has discriminated the equality betweenthe input phase difference signal 6 and the input magnitude of detectionlevel S704. When the magnitude comparator 703 has issued the level 0cross pulse S703, the magnitude comparator 703 issues the level 0 crosspulse S703 as an output to the timing control circuit 707 and the locussorting circuit 710. Here, the level setting circuit 704 has a level 0corresponding to the phase difference of π/2 set as the magnitude ofdetection level S704 (refer to FIG. 6a and FIG. 7 which will bespecifically described hereinbelow).

The locus sorting circuit 710 is composed of the timer circuit 705 andthe discriminating circuit 706. The locus sorting circuit 710discriminates and sorts the locus of a change in the phase differencesignal 6 on the basis of the level 1 cross pulse S701 and the level 0cross pulse S703. Then, the locus sorting circuit 710 generates a timingadjusting signal S706 corresponding to the discriminated sort as anoutput to the timing control circuit 707.

To the timer circuit 705 are applied the level 1 cross pulse S701 andthe level 0 cross pulse S703. The timer circuit 705 starts the timercounting when it has received either of the level 1 cross pulse S701 andthe level 0 cross pulse S703 as an input. Then, the timer circuit 705causes the timer to cease the counting when either of the level 1 crosspulse S701 and the level 0 cross pulse S703 is introduced as an inputwithin a fixed interval after the start of the timer counting. Here, oneand the same pulse may be used for starting and terminating the timercounting. For example, the level 0 cross pulse S703 may be applied tostart the timer counting and the level 0 cross pulse S703 may be alsoapplied to terminate the timer counting. There are times when the pulsefor terminating the timer counting is not applied within the fixedinterval after the pulse for starting the timer counting has beeninjected. The timer circuit 705, therefore, is so constructed that thetimer counting may be automatically terminated and reset after theelapse of the fixed interval. Then, the timer circuit 705 issues a countdata (time counted) S705 as an output to the discriminating circuit 706and resets the timer.

Here, the timer circuit 705 resets the timer with the level 0 crosspulse S701 and starts the clocking all over again from the beginningwhen the first pulse to be applied after the application of the level 0cross pulse S701 happens to be the level 0 cross pulse S701.

The timer circuit 705 resets the timer with the level 1 cross pulse S703and starts the clocking all over again from the beginning when the firstpulse to be applied after the application of the level 1 cross pulseS703 happens to be the level 1 cross pulse S703.

To the discriminating circuit 706 is applied the count data S705. Thediscriminating circuit 706 determines whether or not the input countdata S705 satisfies any of the conditions for detection stored inadvance in the discriminating circuit 706 (refer to FIG. 6a which willbe specifically described hereinbelow). Then, the discriminating circuit706 generates as an output to the timing control circuit 707 the timingadjusting signal S706 which corresponds to the condition of detectionfound to be satisfied by the input count data S705.

To the timing control circuit 707 are applied the level 1 cross pulseS701, the level 0 cross pulse S703, and the timing adjusting signalS706. The timing control circuit 707 generates a clock recovery signalS707 as an output to the DPLL circuit 72 in accordance with the inputtiming adjusting signal S706 (refer to FIG. 6a which will be describedspecifically hereinbelow).

Now, the operations of the circuits within the clock recovery signalgenerating circuit 71A will be described and, through the description ofthese operations, the functions of the timer circuit 705, thediscriminating circuit 706, and the timing control circuit 707 will bedelineated.

In the first example, the two detection levels of level 0 and level 1are set in the level setting circuit. The magnitude comparatorsseverally issue a pulse at the moment that the phase difference signal 6becomes equal to the magnitude of detection level. The locus sortingcircuit 710 estimates what sort of a locus has been described by thephase difference signal 6 on the basis of the state of application ofthe pulse. In accordance with the estimated locus, the timing controlcircuit 707 selects the time preceding the generation of the clockrecovery signal S707. The timing control circuit 707 effects thegeneration of the clock recovery signal S707 in accordance with theresult of the selection. The first example operates by this method.

Here, the two magnitudes of detection level are the level 1 detectionlevel S702 corresponding to the phase difference of 0 and the level 0detection level S704 corresponding to the phase difference of π/2. Themagnitude of detection level S702 is set in the level setting circuit702 and the magnitude of detection level S704 in the level settingcircuit 704.

To the magnitude comparator 701 are applied the phase difference signal6 and the magnitude of detection level S702. The magnitude comparator701 determines whether or not the phase difference signal 6 equals thedetection level S702. When it has determined that the phase differencesignal 6 and the magnitude of detection level S702 are equal, themagnitude comparator 701 generates the level 1 cross pulse S701. Then,the magnitude comparator 701 emits the level 1 cross pulse S701 sogenerated as an output to the timing control circuit 707 and the locussorting circuit 710. When the magnitude comparator 701 has determinedthat the phase difference signal 6 and the magnitude of detection levelS702 are not equal, it does not generate the level 1 cross pulse S701.

To the magnitude comparator 703 are applied the phase difference signal6 and the detection level S704. The magnitude comparator 703 determineswhether or not the phase difference signal 6 and the magnitude ofdetection level S704 are equal. When the magnitude comparator 703 hasdetermined that the phase difference signal 6 and the magnitude ofdetection level S704 are equal, it generates the level 0 cross pulseS703. Then, the magnitude comparator 703 emits the level 0 cross pulseS703 so generated as an output to the timing control circuit 707 and thelocus sorting circuit 710. When the magnitude comparator 703 hasdetermined that the phase difference signal 6 and the magnitude ofdetection level S704 are not equal, it does not generate the level 0cross pulse S703.

Now, the data to be used in the present invention will be describedbelow with reference to FIG. 5.

The data is composed of a preamble part, a UW part, and a data proper.

The preamble part has the input of a preamble pattern. For example, ithas the input of repetitions of "1001" in such a manner as "10011001 . .. 1001."

The UW part has the input of a sign designating the head of a data.

The data proper has the input of a data which is desired to betransmitted.

FIG. 6a and FIG. 7 are diagrams showing the operations of the locussorting circuit 710 and the timing control circuit 707 in the firstexample.

The time T denotes the duration of an operation equivalent to one symbolof data (time equal to 360°).

The fixed time Td denotes the duration of an operation for determiningwhether or not the phase difference signal 6 is a pulse in the period ofpreamble (time equal to 150°, for example).

The time t0 denotes the duration of an operation enabling the timingcontrol circuit 707 to adjust the timing of emitting the clock recoverysignal S707 (time equal to 60°, for example).

Now, the method for estimating the locus of the phase difference signal6 will be described below with reference to FIG. 6a. FIG. 6a is adiagram showing the operations of the timer circuit 705 and thediscriminating circuit 706 of the locus sorting circuit 710.

Detection No. 1 is obtained only when the conditions shown in 1 to 5below are wholly satisfied sequentially in the-order mentioned.

1. The timer circuit 705 admits the level 0 cross pulse S703 as aninput.

2. The timer circuit 705 starts counting (clocking time).

3. The timer circuit 705 admits the level 1 cross pulse S701 as aninput.

4. The timer circuit 705 terminates the counting (clocking of time).

5. The discriminating circuit 706 compares the count data (clockreading) S705 with the fixed time Td set in advance and finds that thecount data is shorter than the fixed time Td.

When Detection No. 1 is obtained, the discriminating circuit 706generates the timing adjusting signal S706 as an output to the timingcontrol circuit 707. Then, after the elapse of the time |t0+T/2|following the time of application of the level 0 cross pulse S703 intothe locus sorting circuit 710, the timing adjusting signal S706 causesthe timing control circuit 707 to issue the clock recovery signal S707to the DPLL circuit 72.

Detection No. 2 is obtained only when the conditions shown in 1 to 5below are wholly satisfied sequentially in the order mentioned.

1. The timer circuit 705 admits the level 1 cross pulse S701 as aninput.

2. The timer circuit 705 starts counting (clocking time).

3. The timer circuit 705 admits the level 0 cross pulse S703 as aninput.

4. The timer circuit 705 terminates the counting (clocking of time).

5. The discriminating circuit 706 compares the count data (clockreading) S705 with the fixed time Td set in advance and finds that thecount data (clock reading) S705 is shorter than the fixed time Td.

When Detection No. 2 is obtained, the discriminating circuit 706 emitsthe timing adjusting signal S706 as an output to the timing controlcircuit 707. Then, after the elapse of the time |t0+T/2| following thetime of injection of the level 1 cross pulse S703 into the locus sortingcircuit 710, the timing adjusting signal S706 causes the timing controlcircuit 707 to issue the clock recovery signal S707 to the DPLL circuit72.

Detection No. 3 is obtained only when the conditions shown in 1 to 3below are wholly satisfied sequentially in the order mentioned.

1. The timer circuit 705 admits the level 1 cross pulse S701 as aninput.

2. The timer circuit 705 starts counting (clocking time).

3. The timer circuit 705 does not admit the level 0 cross pulse S703within the fixed time Td.

When Detection No. 3 is obtained, the discriminating circuit 706generates the timing adjusting signal S706 as an output to the timingcontrol circuit 707. Then, after the elapse of the time |T/2| followingthe time of injection of the level 1 cross pulse S703 into the locussorting circuit 710, the timing adjusting signal S706 causes the timingcontrol circuit 707 to issue the clock recovery signal S707 to the DPLLcircuit 72.

FIG. 7 is an explanatory diagram of the sortation of loci of the phasedifference signal (detection of locus) and an explanatory diagram of theadjustment of the output timing of the clock regenerating pulse shown inFIG. 5.

The bold line in FIG. 7a represents the same locus "10011001 . . . 1001"of the phase difference signal 6 during the period of preamble as shownin FIG. 20a. In the case of the π/4-shift QPSK signal, it is not themagnitude of phase difference itself of the phase difference signal 6but the locus of the phase difference signal 6 that represents datavalue.

Here, π, π/2, π/4, 0, -π/2, and -π in the vertical axis of the graphdenote magnitudes of phase difference. In FIG. 7a, the times a and erepresent intersections of the phase difference signal 6 and the phasedifference π/2 during the period of preamble. The times b and drepresent intersections of the phase difference signal 6 and the phasedifference 0 during the period of preamble.

First, the case in which Detection No. 1 is obtained will be describedbelow with reference to FIG. 7a.

The phase difference signal 6 crosses the detection level magnitude atthe time a during the period of preamble. Then, the timer circuit 705 ofthe locus sorting circuit 710 admits the level 0 cross pulse S703 as aninput from the magnitude comparator 703 and starts counting. Then, thephase difference signal 6 during the period of preamble crosses thedetection level magnitude at the time b. The timer circuit 705consequently admits the level 1 cross pulse S701 as an input from themagnitude comparator 701 within the fixed time Td from the time point aand terminates the counting (at the time point b). Here, thediscriminating circuit 705 determines that the count data S705 isshorter than the fixed time Td. Detection No. 1 is obtained inconsequence of the operation described above.

At the time c which terminates the duration of |t0+t/2| starting fromthe time a, the discriminating circuit 706 generates as an output to thetiming control circuit 707 the timing adjusting signal S706 instructingthe clock recovery signal S707 as an output to the DPLL circuit 72(refer to FIG. 7b).

Then, the case in which Detection No. 2 is obtained will be describedbelow with reference to FIG. 7a.

The phase difference signal 6 during the period of preamble crosses thedetection level magnitude at the time d. As a result, the timer circuit705 of the locus sorting circuit 710 admits the level 1 cross pulse S701as an input from the magnitude comparator 701 and starts counting. Then,the phase difference signal 6 during the period of preamble crosses thedetection level magnitude at the time e. As a result, the timer circuit705 admits the level 0 cross pulse S703 as an input from the magnitudecomparator 703 within the fixed time Td from the time d and terminatesthe counting (at the time e). Here, the discriminating circuit 705determines that the count data S705 is shorter than the fixed time Td.Detection No. 2 is obtained in consequence of the operation describedabove.

At the time point f which terminates the duration of |t0+T/2| startingfrom the time d, the discriminating circuit 706 generates as an outputto the timing control circuit 707 the timing adjusting signal S706instructing the clock recovery signal S707 as an output to the DPLLcircuit 72 (refer to FIG. 7b).

Similarly thence, the phase difference signal 6 during the period ofpreamble adapts the locus sorting carrier 710 for the adjustment oftiming of Detection No. 1 and Detection No. 2. Then, from the timingcontrol circuit 707, the clock recovery signal S707 is emitted at such atiming that the eye pattern may be opened to the widest extent asillustrated in FIG. 7b (at the time points of c and f). As a result, aclock signal of a correct phase synchronized with this pulse isgenerated from the DPLL 72 as shown in FIG. 7c.

Here, the jitter 6 is set at 0 as shown in FIG. 20b. Then, the clockrecovery signal of FIG. 7b is compared with the clock recovery signal ofFIG. 20b. It is consequently found that during the period of preamble,the phase of the clock recovery signal S707 given to the DPLL 72 isvaried with an increment of T/2. The DPLL 72, however, is capable ofeasily coping with this difference by advancing the phase discriminationwithin the DPLL 72 with an increment of T/2.

When the period of preamble terminates and the period of UW or that ofdata proper sets in, the bit pattern is no longer fixed. As a result,the phase difference signal 6 assuming any of a total of 16 foci isapplied as an input to the clock recovery signal generating circuit 71A.Detection No. 1 and Detection No. 2 mentioned above have due respectpaid to the loci particularly during the period of preamble. Even duringthe period of UW or that of data proper, the assumption of such loci asare related to Detection No. 1 and Detection No. 2 possibly arises. Theloci related to Detection No. 3 correspond to the period of UW and thatof data proper. The number of loci along which the adjustment of timingis effected by Detection No. 3 is 8 as described specificallyhereinafter.

FIG. 8a, FIG. 8b, FIG. 8c, FIG. 8d, and FIG. 8e aid in the descriptionof the relation of the total of 16 loci and the adjustment of outputtiming of the clock recovery pulse. Now, the relation between the lociof the phase difference signal 6 and the adjustment of timing will bedescribed below with reference to FIG. 8a, FIG. 8b, FIG. 8c, FIG. 8d,and FIG. 8e. For the sake of convenience of the explanation, the totalof 16 loci are depicted as divided in five diagrams.

In FIG. 8a, the two locus patterns 8a-1 and 8a-2 are indicated each witha bold line.

First, the locus pattern 8a-1 will be explained. The timer circuit 705of the locus sorting circuit 710 admits the level 0 cross pulse S703 asan input from the magnitude comparator 703 and starts counting (at thetime point g). Then, within the fixed time Td from the time point g, thetimer circuit 705 admits the level 1 cross pulse S701 as an input fromthe magnitude comparator 701 and terminates the counting (at the timepoint h). The discriminating circuit 705 determines that the count dataS705 is shorter than the fixed time Td. Detection No. 1 (refer to FIG.6a) is obtained in consequence of the operation described above.

After the elapse of the time |t0+T/2| from the time point g, thediscriminating circuit 706 emits the timing adjusting signal S706 as anoutput to the timing control circuit 707.

In the same manner as described above with respect to the period ofpreamble, the timing control circuit 707 undergoes the adjustment oftiming by the locus sorting circuit 710 and, in consequence thereof,emits the clock recovery signal S707 at such a timing that the eyepattern may be opened to the widest extent.

Now, the locus pattern 8a-2 will be explained below. The timer circuit705 of the locus sorting circuit 710 admits the level 1 cross pulse S701as an input from the magnitude comparator 701 and starts counting (atthe time i). Then, within the fixed time Td from the time i, the timercircuit 705 admits the level 0 cross pulse S703 as an input from themagnitude comparator 703 and terminates the counting (at the time j).The discriminating circuit 705 determines that the count data S705 isshorter than the fixed time Td. Detection No. 2 (see FIG. 6a) isobtained in consequence of the operation described above.

Then, after the elapse of the time |t0+T/2| from the time i, thediscriminating circuit 706 generates the timing adjusting signal S706 asan output to the timing control circuit 707.

In the same manner as described above with respect to the period ofpreamble, the timing control circuit 707 undergoes the adjustment oftiming by the locus sorting circuit 710 and, in consequence thereof,generates the clock recovery signal S707 at such a timing that the eyepattern may be opened to the widest extent.

In FIG. 8b, the six locus patterns 8b-1, 8b-2, 8b-3, 8b-4, 8b-5, and8b-6 are indicated each with a bold line.

None of these locus patterns crosses either the 0 or the 1 detectionlevel. In this case, none of the conditions for detection indicated forDetection No. 1 through No. 3 in FIG. 6a is applicable. Thus, theadjustment of timing by the locus sorting circuit 710 is not carried outon any of these locus patterns. Then, the timing control circuit 707does not generate the clock recovery signal S707.

In FIG. 8c, the two locus patterns 8c-1 and 8c-2 are indicated each witha bold line.

Now, the two locus patterns 8c-1 and 8c-2 will be explained below. Thetimer circuit 705 of the locus sorting circuit 710 admits the level 0cross pulse S703 as an input from the magnitude comparator 703 andstarts counting (at the time point k). Within the fixed time Td from thetime point k, however, neither of these two locus patterns 8c-1 and 8c-2crosses either the 0 or the 1 detection level S702 or S704. Thus, noneof the conditions for detection indicated for Detection No. 1 throughNo. 3 in FIG. 6a is applicable. Thus, the adjustment of timing by thelocus sorting circuit 710 is not carried out on either of these twolocus patterns 8c-1 and 8c-2. Then, the timing control circuit 707 doesnot generate the clock recovery signal S707.

In FIG. 8d, the four locus patterns 8d-1, 8d-2, 8d-3, and 8d-4 areindicated each with a bold line.

Now, the four locus patterns 8d-1, 8d-2, 8d-3, and 8d-4 will beexplained below. The timer circuit 705 of the locus sorting circuit 710admits the level 1 cross pulse S701 as an input from the magnitudecomparator 701 and starts counting (at the time points l, m, and n).Within the fixed time Td from the relevant time points (l, m, and n),however, none of the four locus patterns 8d-1, 8d-2, 8d-3, and 8d-4crosses either of the 0 and the 1 detection level S702 or S704.

The present case falls under the condition of detection of Detection No.3 of FIG. 6a. The timing control circuit 707, therefore, undergoes theadjustment of timing effected by the locus sorting circuit 710. Then,the timing control circuit 707 generates the clock recovery signal S707after the elapse of the fixed time T/2 from the times (l, m, and n) ofcrossing.

Here, the timing control circuit 707 generates the clock recovery signalS707 with respect to the two most gradually inclined locus patterns 8d-1and 8d-2 in all the four locus patterns 8d-1, 8d-2, 8d-3, and 8d-4 asshown in FIG. 8d at such a timing that the eye pattern may be opened tothe widest extent. Then, the timing control circuit 707 generates theclock recovery signal S707 deviated by a fixed amount (jitter ±δ1) fromthe time at which the eye pattern is opened to the widest extent withrespect to the other two most sharply inclined locus patterns 8d-3 and8d-4.

In FIG. 8e, the two locus patterns 8e-1 and 8e-2 are indicated each witha bold line. Neither of these locus patterns represents a signal duringthe period of preamble.

First, the locus pattern 8e-1 will be explained below. The timer circuit705 of the locus sorting circuit 710 admits the level 0 cross pulse S703as an input from the magnitude comparator 703 and starts counting (atthe time o). Then, within the fixed time Td from the time o, the timercircuit 705 admits the level 1 cross pulse S701 as an input from themagnitude comparator 701 and terminates the counting (at the time p. Thediscriminating circuit 705 then determines that the count data S705 isshorter than the fixed time Td. Detection No. 1 (refer to FIG. 6a) isobtained in consequence of the operation described above.

Then, after the elapse of the time |t0+T/2| from the time o, thediscriminating circuit 706 generates the timing adjusting signal S706 asan output to the timing control circuit 707.

Now, the locus pattern 8e-2 will be explained below. The timer circuitof the locus sorting circuit 710 admits the level 1 cross pulse S701 asan input from the magnitude comparator 710 and starts counting (at thetime p). Then, within the fixed time from the time point p, the timercircuit 705 admits the level 0 cross pulse S703 as an input from themagnitude comparator 703 and terminates the counting (at the time q).The discriminating circuit 705 determines that the count data S705 isshorter than the fixed time Td. Detection No. 2 (refer to FIG. 6a) isobtained in consequence of the operation described above.

Then, after the elapse of the time |t0+T/2| from the time p, thediscriminating circuit 706 emits the timing adjusting signal S706 as anoutput to the timing control circuit 707.

These locus patterns, however, invariably produce a latter cross earlieror later than the locus patterns which mainly occur during the period ofpreamble shown in FIG. 7a. Thus, the time at which the clock recoverypulse is generated is deviated by a fixed amount (jitter ±δ2) from themost desirable time at which the eye pattern is opened to the widestextent.

In the clock recovery signal generating circuit 71A of the firstexample, the clock recovery signal S707 having no jitter can beextracted perfectly and applied into the DPLL 72 during the reception ofthe pattern of the period of preamble as described above. Further, theclock signal generated from the DPLL 72 can be quickly led in at acorrect phase angle and this correct phase angle can be stablymaintained.

Even after the pattern of the period of preamble has ceased to exist,the clock recovery signal generating circuit 71A of the first examplecan extract the clock recovery pulse with a probability of 1/2 (8 out of16 chances) and inject it into the DPLL 72. Then, the clock recoverysignal generating circuit 71A can be utilized for the control of thephase of the clock signal generated from the DPLL 72. The clock recoverypulses which are extracted as described above include those havingjitters with a probability of 1/2 (4 out of 8 chances). Even when theDPLL 72 happens to utilize such a clock recovery pulse as entails ajitter, this clock recovery pulse amply functions in following the inputsignal because the phase error between the regenerated clock signal andthe input signal has been fully minimized during the period of preamble.

The clock recovery signal generating circuit 71A described above,therefore, attains detection of the phase of the phase difference signal6 by utilizing the cross phase relative to the plurality of detectionlevels (detection axes). Further, the clock recovery signal generatingcircuit 71A mentioned above is so adapted as to generate clock recoverypulses having no jitter. The clock recovery signal generating circuit71A, therefore, is capable of quickly and correctly synchronizing theclock signal with the phase of the input signal during the period ofpreamble. Further, the clock recovery signal generating circuit 71A isgenerating clock recovery signals S707 which have no jitter. As aresult, the clock recovery signal generating circuit 71A is capable ofprecluding the otherwise possible occurrence of the so-called state ofdeadlock. Further, the DPLL 72 is not always required to be providedwith a device capable of precluding the occurrence of the state ofdeadlock.

Besides, the clock recovery signal generating circuit 71A mentionedabove is capable of generating a clock recovery signal S707 with a highprobability even after the period of preamble has terminated. Further,the clock recovery signal generating circuit 71A permits continuousfollow of the clock recovery signal S707. The clock recovery signalgenerating circuit 71A, therefore, can markedly decrease the possibilityof disrupting synchronism from the conventional standard.

As a result, the DPLL 72 is enabled to generate clock signals of idealquality.

Further, the clock recovery signal generating circuit 71A does not needto discriminate the origin of the input signal to the differentialdemodulator between the preamble and the UW or data proper. In addition,the clock recovery signal generating circuit 71A can repress theinevitable increase in the size thereof to the smallest possible extentand, at the same time, has no possibility of imposing any burden on anexternal microprocessor.

The clock recovery signal is generated in consequence of the operationdescribed above.

Now, the second example of the clock recovery signal generating circuitof this invention will be described in detail below with reference tothe drawings. FIG. 9 is a block diagram illustrating in detail theconstruction of the second example.

A clock recovery circuit is composed of a clock recovery signalgenerating circuit 71B and a DPLL circuit 91.

The clock recovery signal generating circuit 71B is composed of themagnitude comparators 701 and 703, the level setting circuits 702 and704, a locus sorting circuit 710A, the timing control circuit 707, and aphase difference discriminating circuit 93. The locus sorting circuit710A is composed of the timer circuit 705, the discriminating circuit706, and a gate circuit 92. Here, the magnitude comparator 701 and thelevel setting circuit 702 are disposed correspondingly and the magnitudecomparator 703 and the level setting circuit 704 are similarly disposedcorrespondingly in the same manner as in the first example.

The DPLL circuit 91 is adapted to switch the low-speed mode foreffecting the follow of a phase at a low speed and the high-speed modefor effecting the follow of a phase at a high speed, depending on themagnitude of the phase difference between the clock recovery signal S707and the generated clock signal. Incidentally, one example of the DPLL 91of this performance is disclosed in JP-A-61-265,922.

Now, the construction of the clock recovery signal generating circuit71B will be explained below.

The magnitude comparators 701 and 703 and the level setting circuits 702and 704 are identical in construction with those used in the clockrecovery signal generating circuit 71A of the first example.

The locus sorting circuit 710A is composed of the timer circuit 705, thediscriminating circuit 706, and the gate circuit 92.

To the gate circuit 92 are applied the level 0 cross pulse S703generated from the magnitude comparator 703 and a mode signal S93generated from the phase difference discriminating circuit 93. Here, themode signal S93 in the gate circuit 92 is utilized as a signal forcontrolling the output of the level 0 cross pulse S703. Then, the gatecircuit 92 issues the level 0 cross pulse S703 as an output to the timercircuit 705 when the mode signal S93 designates the high-speed controlmode. The gate circuit 92 does not pass the level 0 cross pulse S703 tothe timer circuit 705 when the mode signal S93 designates the low-speedcontrol mode. Here, the high-speed control mode refers to the state ofDetection No. 1 to No. 3 described in the first example (refer to FIG.6a and FIG. 10). The low-speed control mode refers to the state ofDetection No. 4. Detection No. 4 denotes the state in which the timingcontrol circuit 707 emits the clock recovery signal S707 after theelapse of the time |T/2| from the time at which the gate circuit 92admits the level 1 cross pulse S701 as an input from the magnitudecomparator 701 (refer to FIG. 10).

To the timer circuit 705 are applied the level 1 cross pulse S701 andthe level 0 cross pulse S703.

The discriminating circuit 706 is identical in construction with thediscriminating circuit described in the first example and also identicalin operation therewith.

The timing control circuit 707 is identical in construction with thetiming control circuit described in the first example and also identicalin operation therewith. The timing control circuit 707 emits the clockrecovery signal S707 as an output to the DPLL circuit 91 and the phasedifference discriminating circuit 93.

To the phase difference discriminating circuit 93 are applied the clockrecovery signal S707 and a clock signal S91. These signals are used forthe determination of phase difference.

Also in the clock recovery signal generating circuit 71B of the secondexample, the operation of Detection No. 1 or No. 2 in the high-speedcontrol mode is proceeding during the reception of the period ofpreamble. The clock recovery signal generating circuit 71B is capable ofextracting a jitter-free clock recovery pulse perfectly and inject itinto the DPLL circuit 91. As a result, the clock recovery signalgenerating circuit 71B can quickly lead in the phase of the clock signalS91 generated from the DPLL circuit 91 in a correct phase angle.

When the clock signal S91 is drawn in at a desired phase angle (withinπ/4, for example) during or after the period of preamble as describedabove, the high-speed control mode is switched to the low-speed controlmode by the phase difference discriminating circuit 93.

The locus sorting circuit 710A, therefore, executes the operation ofDetection No. 4 based exclusively on the level 1 cross pulse. At thesame time, the DPLL circuit 91 also switches to the low-speed controlmode and carries out the control of the generated phase of the clocksignal S91 at a low speed so as to maintain the stabilized statethereof.

The present second example likewise contemplates detecting the phase inthe phase difference signal 6 by utilizing the cross phase relative tothe plurality of detection levels (detection axes) and consequentlygenerating the clock regenerating signal S707. The clock recoverycircuit, therefore, is capable of quickly and correctly synchronizingthe clock signal S91 with the phase of the input signal during theperiod of preamble. Further, the clock recovery circuit can continuouslygenerate and follow the clock recovery signal S707 with a high degree ofprobability even after the termination of the period of preamble and canmarkedly reduce the possibility of disrupting synchronism. Since thecontrol of phase is effected at a low speed after the clock signal S91has been led into the phase of the input signal, the clock signal S91acquires a stable phase substantially regardless of the possibility thatthe magnitude comparator 701 or 703 will generate a pulse in response tosuch an extraneous signal as noise.

The second example, therefore, can meet the contradictory demands, i.e.quick entrance of clock and stable recovery of clock, moresatisfactorily than the first example.

The examples cited thus far represent cases of using two detectionlevels (detection axes) for the estimation of loci of a phase differencesignal. The present invention does not need to be limited to thesecases. It allows use of three or more detection levels when necessary.In this case, the number of sorts of locus (kinds of control of thetiming control circuit 707) may be selected so as to suit the number ofdetection levels.

The examples cited above also represent cases of resorting to theprecondition that the pattern of the period of preamble should berepetitions of "1001." This invention allows use of other preamblepatterns. In this case, the sortation of loci and the adjustment ofoutput timing of the clock recovery pulses may be implemented inconformity with the particular preamble pattern to be adopted.

Now, the third example of the clock recovery signal generating circuitof this invention will be described in detail below with reference tothe drawings. FIG. 11 is a block diagram illustrating in detail theconstruction of the third example.

The clock recovery circuit is composed of a clock recovery signalgenerating circuit 71C and the DPLL circuit 72.

The clock recovery signal generating circuit 71C is composed ofmagnitude comparators 1101, 1103, 1105, and 1107, level setting circuits1102, 1104, 1106, and 1108, pulse synthesizing circuits 1109 and 1110, alocus sorting circuit 710B, and the timing circuit 707. The locussorting circuit 710B is composed of a timer circuit 1111 and adiscriminating circuit 1112. Here, the magnitude comparator 1101 and thelevel setting circuit 1102, the magnitude comparator 1103 and the levelsetting circuit 1104, the magnitude comparator 1105 and the levelsetting circuit 1106, and the magnitude comparator 1107 and the levelsetting circuit 1108 are severally disposed correspondingly.

The DPLL circuit 72 is identical in construction with the circuitdescribed in the first example and also identical in operationtherewith.

Now, the construction and operation of the clock recovery signalgenerating circuit 71C will be described below.

To the magnitude comparator 1101 are injected the phase differencesignal 6 and a magnitude of detection level S1102 issued from the levelsetting circuit 1102. The magnitude comparator 1101 determines whetheror not the phase difference signal 6 admitted therein changes in thedirection of π→-π and also determines whether or not the input phasedifference signal 6 is equal to the magnitude of detection level S1102.The magnitude comparator 1101 generates a pulse S1101 only when theinput phase difference signal 6 satisfies the conditions mentionedabove. The magnitude comparator 1101 emits the generated pulse S1101 asan output to the pulse synthesizing circuit 1109 and the discriminatingcircuit 1112 of the locus sorting circuit 710B. Here, the level settingcircuit 1102 has level 1 corresponding to the phase difference 0 set asthe magnitude of detection level S1102 (refer to FIG. 13a). Themagnitude of detection level S1102 in this case represents the case inwhich the phase difference signal 6 has changed in the direction of fromπ to -π. The magnitude comparator 1101, therefore, generates the pulseS1101 when the phase difference signal 6 has changed in the direction offrom π to -π and has crossed the magnitude of detection level S1102(refer to FIG. 13b).

To the magnitude comparator 1103 are applied the phase difference signal6 and the magnitude of detection level S1104 generated from the levelsetting circuit 1104. The magnitude comparator 1103 determines whetheror not the phase difference signal 6 admitted therein changes in thedirection of -π→π and, at the same time, determines whether or not theinput phase difference signal 6 is equal to the magnitude of detectionlevel S1104. The magnitude comparator 1103 generates a pulse S1103 onlywhen the phase difference signal 6 admitted therein satisfies theconditions mentioned above. Then, the magnitude comparator 1103 emitsthe generated pulse S1103 as an output to the pulse synthesizingcircuits 1109 and 1110. Here, the level setting circuit 1104 has level 1corresponding to the phase difference 0 set as the magnitude ofdetection level S1104 (refer to FIG. 13a). The magnitude of detectionlevel S1104 of the level setting circuit 1104 represents the case inwhich the phase difference signal 6 has changed in the direction of from-π to π. The magnitude of detection level S1104 in this case denotes thechange of the phase difference signal 6 in the direction of from -π toπ. The magnitude comparator 1103, therefore, generates the pulse S1103when the phase difference signal 6 has changed in the direction of from-π to π and has crossed the magnitude of detection level S1104 (refer toFIG. 13c).

To the magnitude comparator 1105 are injected the phase differencesignal 6 and the magnitude of detection level S1106 issued from thelevel setting circuit 1106. The magnitude comparator 1105 determineswhether or not the phase difference signal 6 admitted therein changes inthe direction of π→-π and, at the same time, determines whether or notthe input phase difference signal 6 is equal to the magnitude ofdetection level S1106. The magnitude comparator 1105 generates the pulseS1105 only when the input phase difference signal 6 satisfies theconditions mentioned above. Then, the magnitude comparator 1105 emitsthe generated pulse S1105 as an output to the pulse synthesizing circuit1110. Here, the level setting circuit 1106 has level 0 corresponding tothe phase difference π/2 set as the magnitude of detection level S1106(refer to FIG. 13a). The magnitude of detection level S1106 of the levelsetting circuit 1106 represents the case in which the phase differencesignal 6 has changed in the direction of from π to -π. The magnitudecomparator 1105, therefore, generates the pulse S1105 when the phasedifference signal 6 has changed in the direction of from π to -π and hascrossed the magnitude of detection level S1106 (refer to FIG. 13d).

To the magnitude comparator 1107 are injected the phase differencesignal 6 and the magnitude of detection level S1108 emitted from thelevel setting circuit 1108. The magnitude comparator 1107 determineswhether or not the phase difference signal 6 admitted therein changes inthe direction of -π→π and, at the same time, determines whether or notthe input phase difference signal 6 is equal to the magnitude ofdetection level S1108. The magnitude comparator 1107 generates the pulseS1107 only when the phase difference signal 6 admitted therein satisfiesthe conditions mentioned above. Then, the magnitude comparator 1107emits the generated pulse S1107 as an output to the discriminatingcircuit 1112 of the locus sorting circuit 710B. Herein, the levelsetting circuit 1108 has level 0 corresponding to the phase differenceπ/2 set as the magnitude of detection level S1108 (refer to FIG. 13a).The magnitude of detection level S1108 of the level setting circuit 1108represents the case in which the phase difference signal 6 has changedin the direction of from -π to π. The magnitude comparator 1107,therefore, generates the pulse S1107 when the phase difference signal 6has changed in the direction of from -π to π and has crossed themagnitude of detection level S1108 (refer to FIG. 13e).

To the pulse synthesizing circuit 1109 are injected the pulse S1101 andthe pulse S1103. The pulse synthesizing circuit 1109 obtains a magnitudeof synthesis S1109 by computing the logical sum of the pulses S1101 andS1103 admitted therein (refer to FIG. 13f). Then, the pulse synthesizingcircuit 1109 emits the magnitude of synthesis S1109 as an output to thetiming control circuit 707.

To the pulse synthesizing circuit 1110 are injected the pulse S1103 andthe pulse S1105. The pulse synthesizing circuit 1110 then obtains amagnitude of synthesis S1110 by computing the logical sum of the pulsesS1103 and S1105 admitted therein (refer to FIG. 13g). Then, the pulsesynthesizing circuit 1110 emits the magnitude of synthesis S1110 as anoutput to the timing circuit 707 and the timer circuit 1111 of the locussorting circuit 710B.

The locus sorting circuit 710B is composed of the timer circuit 1111 andthe discriminating circuit 1112. The operation of the locus sortingcircuit 710B will be explained below with reference to FIG. 14. FIG. 14ashows loci of a phase difference signal. In the diagram, the phasedifference signal during the period of preamble is indicated as (1) andtwo typical phase difference signals not during the period of preambleare indicated as (2) and (3).

To the timer circuit 1111 is applied the magnitude of synthesis S1110.The timer circuit 1111, on admitting the magnitude of synthesis S1110,resets the timer and starts counting (clocking time). Here, the timercircuit 1111 stops automatically after the elapse of a fixed time (timeof Td, in this case) after the start of counting. Then, the timercircuit 1111 emits a count data S1111 (numerical value obtained bycounting) as an output to the discriminating circuit 1112. The countdata S1111 denotes the information representing the elapse of a fixedtime allowed for the counting (time Td in this case).

First, one example of the operation described above will be cited belowwith reference to the phase difference signal (1) during the period ofpreamble. The timer circuit 1111 continues the counting for the durationof the time Td from the time points of r and u and the emission of an Hlevel to the discriminating circuit 1112 for the duration of the time Td(refer to FIG. 14b and c). Similarly, in the case of the phasedifference signal (2) not during the period of preamble, the counting iscontinued for the duration of the time Td from the time point of w.Then, in the case of the phase difference signal (3) not during theperiod of preamble, the counting is continued for the duration of thetime Td from the time point of x. Then, the timer continues the emissionof the H level to the discriminating circuit 1112 for the duration ofthe time Td (refer to FIG. 14f, g, j, and k).

The discriminating circuit 1112 is possessed of an S-E resetdiscriminating part (not shown). Here, the symbol S-E used in the R-Ereset discriminating part stands for START-END. The S-E resetdiscriminating part, on receiving the magnitude of synthesis S1110,retains the state of H level and, on receiving the pulse S1101 or pulseS1107, retains the state of L level. To the discriminating circuit 1112are applied the count data 1111, the pulse S1101, and the pulse S1107.The discriminating circuit 1112 determines whether or not the count dataS1111 and the pulse S1101 and the pulse S1107 so admitted thereinsatisfy the conditions of detection described above in the first exampleof the clock recovery signal generating circuit of this invention (referto FIG. 6b).

Now, the operation of the discriminating circuit 1112 will be explainedbelow with reference to FIG. 14. The counting of the time Td is startedwhen the pulse crossing the level 0 has a minus inclination and when thepulse crossing the level 1 has a plus inclination.

First, the case in which the phase difference signal (1) during theperiod of preamble is applied in the discriminating circuit 1112 will beexplained below with reference to FIG. 14b, c, d, and e. The S-E resetdiscriminating part omitted from illustration herein starts retainingthe H level (time points of r and u) when the magnitude of synthesisS1110 is applied into the timer circuit 1111 (time points of d1 and d2)to set the timer counting. Then, the S-E reset discriminating partstarts retaining the L level (time points of s and v) when it admits thepulse S1101 or pulse S1107. Here, the discriminating circuit 1112examines the state which the S-E reset discriminating part omitted fromillustration herein assumes when the count data S1111 admitted thereinhas changed from the H level to the L level (namely when the counting ofthe time Td is completed). When the S-E reset discriminating part isfound to be retaining the L level, the discriminating circuit 1112selects the magnitude of synthesis S1110 in the timing control circuit707 (Detection No. 1 and No. 2 shown in FIG. 6b). Here, the S-E resetdiscriminating part not shown herein receives the pulse S1101 (timepoint of s), the discriminating circuit 1112 emits as an output to thetiming control circuit 707 a timing adjusting signal S1112 whichinstructs emission of a level 0 cross timing at the time point of e1following the elapse of the time |t0+T/2| from the time point of d1(Detection No. 1 shown in FIG. 6b). Then, the timing control circuit 707retains the state of the level 0. When the S-E reset discriminating partnot shown herein admits the pulse S1107 as an input (at the time pointof v), the discriminating circuit 1112 at the time point of e2 after theelapse of the time t0+T/2 from the time point of d2 emits the timingadjusting signal S1112 instructing emission of the level 1 cross timingas an output to the timing control circuit 707 (Detection No. 2 shown inFIG. 6b). Then, the timing control circuit 707 retains the state oflevel 1.

Now, the case in which the phase difference signal (2) not during theperiod of preamble is applied as an input into the discriminatingcircuit 1112 will be explained below with reference to FIG. 14f, g, h,and i. When the magnitude of synthesis S1110 is applied into the timercircuit 1111 (at the time point of h1) and the timer is set counting,the S-E reset discriminating part not shown herein retains the H level(at the time point of w). Since neither the pulse S1101 nor the pulseS1107 is applied into the S-E reset discriminating part not shownherein, however, the S-E reset discriminating part continues retainingthe H level. When the counting of the time Td is completed, thediscriminating circuit 1112 examines the state retained by the S-E resetdiscriminating part not shown herein. Since the S-E reset discriminatingpart not shown herein retains the H level, the discriminating circuit1112 selects the magnitude of synthesis S1109 in the timing controlcircuit (Detection No. 3 shown in FIG. 6b). Then, the discriminatingcircuit 1112 at the time after the elapse of the time | T/2| from thetime h1 generates the timing adjusting signal S1112 instructinggeneration of the level 1 cross timing as an output to the timingcontrol circuit 707 (Detection No. 3 shown in FIG. 6b). Here, the pulsesynthesizing circuit 1109 has not detected the level 1. The timingcontrol circuit 707 is not retaining the level 0. The timing controlcircuit 707, therefore, is incapable of generating the level 1 crosstiming (FIG. 14i). Here, the timing control circuit 707 retains theformer state.

Now, the case in which the phase difference signal (3) not during theperiod of preamble has been applied into the discriminating circuit 1112will be explained below with reference to FIG. 14j, k, l, and m. Whenthe magnitude of synthesis S1110 is applied into the timer circuit 1111(at the time l1) and the timer is set counting, the S-E resetdiscriminating part not shown herein retains the H level (at the timex). Here, the S-E reset discriminating part not shown herein retains theL level when the pulse S1101 is applied therein (at the time y). Whenthe counting of the time Td is completed, the discriminating circuit1112 examines the state retained by the S-E reset discriminating partnot shown herein. Then, since the S-E reset discriminating part notshown herein is retaining the H level, the discriminating circuit 1112selects the magnitude of synthesis S1109 in the timing control circuit707 (Detection No. 3 shown in FIG. 6b). At the time m1 after the elapseof the time |T/2| from the time l1, the discriminating circuit 1112generates the timing adjusting signal S1112 instructing the level 1cross timing as an output to the timing control circuit 707 (DetectionNo. 3 shown in FIG. 6b), Then, the timing control circuit 707 retainsthe state of the level 1. It does not count the time Td at the time l2.Since the timing control circuit 707 is retaining the state of the level1 and owing to the fact that the level 1 has been crossed, however, thetiming adjusting signal S1112 instructing the level 1 cross timing isgenerated as an output to the timing control circuit 707 at the timepoint of m2 after the elapse of the time |T/2| from the time point of l2(Detection No. 3 shown in FIG. 6b).

To the timing control circuit 707 are injected the magnitude ofsynthesis S1119 issued from the pulse synthesizing circuit 1109, themagnitude of synthesis S1110 issued from the pulse synthesizing circuit1110, and the timing adjusting signal S1112 issued from the locussorting circuit 710B. The timing control circuit 707 delays themagnitudes of synthesis S1109 and S1110 by a duration conforming to theinstruction of the timing adjusting signal S1112 and generates the clockrecovery signal S707. At this time, the timing control circuit 707retains the state which has been designated by the timing adjustingsignal S1112. Then, the timing control circuit 707 generates the clockrecovery signal S707 as an output to the DPLL 72.

The clock recovery signal is generated in consequence of the operationdescribed above.

Now, the fourth example of the clock recovery signal generating circuitof this invention will be described in detail below with reference tothe drawings. FIG. 12 is a block diagram illustrating in detail theconstruction of the fourth example.

The clock recovery circuit is composed of a clock recovery signalgenerating circuit 71D and the DPLL circuit 91.

The clock recovery signal generating circuit 71D is composed of themagnitude comparators 1101, 1103, 1105, and 1107, the level settingcircuits 1102, 1104, 1106, and 1108, the pulse synthesizing circuits1109 and 1110, the locus sorting circuit 710B, the timing controlcircuit 707, a gate circuit 1201, and the phase differencediscriminating circuit 93. The locus sorting circuit 710B is composed ofthe timer circuit 1111 and the discriminating circuit 1112. Here, themagnitude comparator 1101 and the level setting circuit 1102, themagnitude comparator 1103 and the level setting circuit 1104, themagnitude comparator 1105 and the level setting circuit 1106, and themagnitude comparator 1107 and the level setting circuit 1108 areseverally disposed correspondingly.

The DPLL circuit 91 is identical in construction with the circuitdescribed above in the second example of the clock recovery signalgenerating circuit of this invention and is also identical in operationtherewith.

Now, the construction and operation of the clock recovery signalgenerating circuit 71D will be explained below.

In FIG. 12, the magnitude comparators 1101, 1103, 1105, and 1107, thepulse synthesizing circuits 1109 and 1110, the timing control circuit707, the locus sorting circuit 710B, and the phase differencediscriminating circuit 93 are identical in both construction andoperation with the circuits of like designations and like referencenumerals described in the examples of the clock recovery signalgenerating circuit of this invention cited above. Here, thediscriminating circuit 1112 of the locus sorting circuit 710B emits thetiming adjusting signal S1112 generated in the discriminating circuit1112 as an output to the gate circuit 1201. The timing control circuit707 emits the clock recovery signal S707 generated in the timing controlcircuit 707 as an output to the DPLL 91 and the phase differencediscriminating circuit 93.

The phase difference discriminating circuit 93, as described above, isidentical in operation with the phase difference discriminating circuit93 described above in the second example of the clock recovery signalgenerating circuit of the present invention. Now, the operation of thephase difference discriminating circuit 93 will be explained below withreference to FIG. 15. To the phase difference discriminating circuit 93are applied the clock recovery pulse S707 issued from the timing controlcircuit 707 and the clock signal S91 issued from the DPLL circuit 91. Tothe phase difference discriminating circuit 93 are applied the presentclock signal (shown in FIG. 15a), the clock signal delayed by π/4 fromthe present clock signal (shown in FIG. 15b), the clock signal advancedby π/4 from the present clock (shown in FIG. 15c), and the clockrecovery pulse S707 issued from the timing control circuit 707 (shown inFIG. 15d). Here, the phase difference discriminating circuit 93discriminates the state of the clock recovery pulse S707 admittedtherein and the state of the present clock signal based on thecombination of the three clock signals admitted therein (shown in FIG.15a, FIG. 15b, and FIG. 15c) (the states (1), (2), (3), (4), (5), (6),(7), and (8) shown in the diagrams). The state (1) represents the casein which the present clock signal assumes the state of L, the clocksignal delayed by π/4 the state H, and the clock signal advanced by π/4the state of L. In terms of the combination of the present clock signal,the clock signal delayed by π4, and the clock signal advanced by π/4 asarranged in the order mentioned, the state (2) represents H·H·L, thestate (3) H·H·H, the state (4) H·L·H, the state (5) L·L·H, the state (6)L·L·L, the state (7) L·H·L, and the state (8) H·H·L. In this case, thephase difference discriminating circuit 93 recognizes the clock recoverypulse S707 in the state (2). Based on the result of this recognition,the phase difference discriminating circuit 93 concludes that the clocksignal S91 has been applied in a desirable phase angle (within π/4, forexample). Then, the phase difference discriminating circuit 93 emits thephase difference discriminating signal S93 designating the low-speedcontrol mode as an output to the gate circuit 1201 and the DPLL circuit91. Here, the phase difference discrimination is effected by the use ofthe signal delayed by π4 and the signal advanced by π/4 from the presentclock signal. The difference does not need to be limited to π4. The sameeffect is obtained by using a difference of π/2, for example.

To the gate circuit 1201 are applied the timing adjusting signal S1112generated from the discriminating circuit 1112 and the phase differencediscriminating signal S93 generated from the phase differencediscriminating circuit 93. The phase difference discriminating signalS93 to be injected is used in two kinds, the one designating thehigh-speed control mode and the other the low-speed control mode. Whenthe phase difference discriminating signal S93 to be applied designatesthe high-speed control mode, the gate circuit 1201 generates the timingadjusting signal S1112 as an output to the timing control circuit 707.When the phase difference discriminating signal S93 designates thelow-speed control mode, the gate circuit 1201 does not generate thetiming adjusting signal S1112 to the timing control circuit 707.

The clock recovery signal is generated in consequence of the operationdescribed above.

The clock recovery signal generating circuit 71D of this inventiongenerates the clock recovery pulse S707 by detecting the phase in thephase difference signal 6 by utilizing the cross phase relative to theplurality of detection levels (detection axes). The clock recoverysignal generating circuit 71D of this invention, therefore, can quicklyand correctly synchronize the clock signal S91 with the phase of theinput signal during the period of preamble and, at the same time, cangenerate the clock recovery pulse S707 with a high probability evenafter the termination of the period of preamble. Then, the clockrecovery signal generating circuit 71D of this invention can continue tofollow the clock recovery pulse S707 and can markedly reduce thepossibility of disrupting synchronism as compared with the conventionalclock recovery signal generating circuit. Further, the clock recoverysignal generating circuit 71D of this invention, after having the clocksignal S91 led into the phase of the input signal, controls the phase ata low speed. Even when the pulse happens to entrain such an extraneoussignal as noise, therefore, the phase of the clock signal S91 isobtained stably irrespectively of the noise.

The fourth example can meet the contradictory demands, i.e. quickentrance of clock and stable regeneration of clock, more satisfactorilythan the third example.

The examples cited above represent cases of using two or four detectionlevels (detection axes) for the estimation of loci of a phase differencesignal. The present invention does not limit the number of detectionlevels to two or four. Three or five or more detection levels may beused when necessary. In this case, the number of sorts of locus (kindsof control of the timing control circuit) may be suitably selected inconformity with the number of detection levels to be adopted.

The examples cited above also represent cases of resorting to theprecondition that the pattern of the period of preamble should berepetitions of "1001." This invention allows use of other preamblepatterns. In this case, the sortation of loci and the adjustment ofoutput timing of the clock recovery pulses may be implemented inconformity with the particular preamble pattern to be adopted.

The clock recovery signal regenerating circuit of this invention findsextensive utility in differential demodulators for the π/4-shift QPSKsignal. The digital mobile communication is not the only use to be foundtherefor.

This invention, as described above, constructs the clock recovery signalgenerating circuit with a plurality of detection axis cross detectingmeans varied in magnitude of detection axis and adapted to detect thetime at which a phase difference signal crosses a detection axis of afixed magnitude, locus sorting means for discriminating and sorting thelocus of a change in the phase difference signal based on the detectiontiming obtained by the relevant detection axis cross detecting means andgenerating a timing adjusting signal in conformity with the result ofthe sorting as an output, and timing control means for obtaining a clockrecovery phase signal by correcting the time detected by any of thedetection axis cross detecting means designated by the timing adjustingsignal with the time designated by the timing adjusting signal. Thisclock recovery signal generating circuit, therefore, is capable ofideally effecting the clock recovery during and after the admission ofthe clock signal.

INDUSTRIAL APPLICABILITY

The differential demodulators which incorporate therein theinstantaneous phase detecting circuit or clock recovery signalgenerating circuit of the present invention are suitable for use inmobile communication systems which support such public services aspolice, flood control, road management, fire prevention, disasterprevention, radio communication among administrative agencies,electricity, gas, and water supply and mobile communication systemswhich promote such independent enterprises as taxicabs, railroads,newspapers, broadcasting systems, MCA land mobile radio communicationsystem, automatic vehicle position indicating systems, home radiostations, specific small-power radio stations, personal radio stations,and amateur radio stations. They are also suitable for use in mobilecommunications systems for such land communication facilities as cartelephones, cordless telephones, public train telephones, land mobileradio data communication systems, and airport mobile radio systems, suchmarine mobile communication facilities as ship telephones, marinesatellite communication systems, and harbor wireless telephone andtelegraph systems, and such aircraft mobile communication systems aspublic airplane telephones.

We claim:
 1. A clock recovery signal generating circuit for generating aclock recovery signal comprising:a plurality of detection axis crossdetecting means varied in magnitude of detection axis admitting a phasedifference signal, for detecting the time at which the phase differencesignal crosses the detection axis of a prescribed magnitude, locussorting means for discriminating and sorting the locus of a change inthe phase difference signal based on the data of timing obtained by thedetection axis cross detecting means and for generating a timingadjusting signal in conformity with the result of the sorting, andtiming control means for generating a clock recovery signal bycorrecting the data of timing obtained by one of the plurality ofdetection axis cross detecting means designated by the timing adjustingsignal with the time designated by the timing adjusting signal.
 2. Aclock recovery signal generating circuit according to claim 1, whereinthe number of the plurality of detection axis cross detecting means isfour, thereby permitting detection of time using two detecting axes. 3.A clock recovery signal generating circuit for generating a clockrecovery signal, which is used to produce a recovered clock signal,based on a phase difference signal, comprising:a plurality of detectionaxis cross detecting means, having respective prescribed magnitudes ofdetection, each for detecting when the phase difference signal crosses adetection axis of a respective prescribed magnitude of detection, andproducing detection timing data indicative thereof; locus sorting meansfor discriminating and sorting a locus of a change in the phasedifference signal based on the detection timing data from the pluralityof detection axis cross detecting means to produce a sorting result, andfor generating a timing adjusting signal based on the sorting result;timing control means for generating the clock recovery signal bycorrecting the detection timing data of one of the plurality ofdetection axis cross detecting means using the timing adjusting signal,the one of the plurality of detection axis cross detecting means beingselected based on the timing adjusting signal; and a phasediscriminating means for detecting when a difference between therecovered clock signal phase and the clock recovery signal phase hasdecreased below a fixed magnitude and indication a detection thereof;wherein the locus sorting means operates exclusively by the use of thedetection timing data obtained by the selected detection axis crossdetecting means when the phase discriminating means has made thedetection.